1. Field of Invention
The present invention relates to a flip-flop, and more particularly, to a high speed, low setup time voltage sensing flip-flop.
2. Description of Related Art
Timing requirements for digital systems increase as operating frequencies increase. As the integration or number of components increases as well as the speed at which they operate increase in circuits, any unnecessary delays must be eliminated.
Traditional flip-flops typically have relatively long clock-to-output (clk-to-Q) delays. The clk-to-Q delay is the time required for the data output to appear on the Q output, once the clock pulse input makes a transition to active. Besides the clk-to-Q delay, another timing concern is the setup time.
Refer to FIG. 1, which shows a circuit diagram of a conventional flip-flop. The flip-flop has a very large clk-to-Q delay (four inverter plus two transmission gates delay). The conventional flip-flop as shown in FIG. 1 also suffers from a large setup time (2 inverters plus 1 transmission gate delay).
In order to overcome the shortcomings and disadvantages of the conventional flip-flop, the invention provides a high-speed, low setup time, voltage-sensing flip-flop.
Refering to FIG. 2, which shows a circuit diagram of a high-speed, low setup time, voltage-sensing flip-flop of an embodiment of the present invention.
The high-speed, low setup time, voltage-sensing flip-flop of an embodiment of the present invention comprises a master stage and a slave stage. The master stage has a data input and a clock input. The slave stage receives two signal lines from the master stage. When the clock input is low, the two input lines to the slave stage are pulled high. This turns on transistors 190 and 200 and precharges the inputs to the slave stage.
When the clock goes high, the pullup transistors in the master stage are turned off which decouples the inputs of the slave stage from the output of the master stage. At this time, if IN is high, the A input to the slave stage is discharged. If IN is low, the B input to the slave stage is discharged. After the two inputs to the slave stage are decoupled from the master stage, any change in the IN signal result in the inputs to the slave stage to float low since the two lines are not pulled high or low. In this way, the inputs to the slave stage are precharged and discharged on every clock cycle. This precharging results in a nearly zero setup time.
Refering in particular to the slave stage in FIG. 2. Since the outputs Q and QB of the slave stage have symmetrical pullup and pulldown circuits, there is no delay difference between the two output signals. This can be compared with the Q output and the QB output of FIG. 1 of the conventional flip-flop. Note that the Q output must pass through an additional inverter. This causes a delay between the two outputs and results in an inferior design. This is an advantage of the present invention over the conventional design.
When both inputs A and B to the slave stage are high, transistors 190 and 200 are on and transistors 130 and 160 are off. This permits transistors 140 and 150 to maintain their logic levels which keeps the Q and QB outputs stable.
When the clock input transitions to a high, the edge of the clock signal causes either the A input or the B input to discharge depending upon the level of the data input IN. The construction of the master stage allows only one of the inputs A or B to discharge each clock transition. Therefore, the Q output and the QB output are complementary logic levels. In the above case, if the IN input is high, the A input is discharged, turning transistor 130 on, and causing the Q output to be pulled up to a logic high and the QB output is a logic low. If the IN input is low, the B input is discharged, turning transistor 160 on, and causing the QB output to be pulled up to a logic high and the Q output to be a logic low.
Since the inputs to the slave stage are precharged during every clock cycle, the voltage-sensing flip-flop of the present invention is very high-speed and has an extremely low setup time. In fact, due to the design of the master and slave stages, the setup time actually approaches zero.
In contrast, the conventional flip-flop has a very large clk-to-Q delay composed of delay from four inverters plus two transmission gates. In addition, the conventional flip-flop also suffers from a large setup time caused by a delay from two inverters plus a transmission gate. Furthermore, the conventional flip-flop has a delay between the Q output and the QB output since the Q output must pass through an additional inverter in order to make the Q output and QB output complementary.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.